System on Chip (SoC) is one kind of system level chip, which generally includes a Central Process Unit (CPU), a bus, various memory controllers and application devices. The memory controller is used for performing data transmission with external memories of the SoC.
The Nandflash controller is a common memory controller, which performs data transmission with an external Nandflash of a chip. The Nandflash includes a buffer and storage area. The size of the buffer is one page, including a main area for storing data and spare area for storing checksum data. Illustrating with examples, the main area in the buffer includes 2048 bytes (that is, 4 sectors). The spare area of the buffer includes 64 bytes, and is divided into 4 small areas. Each small area is used for storing checksum data corresponding to one sector in the main area. Initial storage location of each sector in the main area, and initial storage location of each area in the spare area are identified with a sector address. Size of above storage area is configured as an integral multiple of the size of the buffer according to actual requirement. Taking one page as a basic storage unit, the initial storage location of each page is identified with a page address.
The data transmission flow between the Nandflash controller and the Nandflash is as follows.
1) Data Transmission in the Write Operation;
FIG. 1a is a flow chart illustrating a method for writing data in the prior art.
Block 1: The Nandflash controller receives a write operation command and command parameters from the CPU. The write operation command indicates that the current transmission type is the write operation, and the command parameters configured by the CPU includes a main address and a spare address.
In the block, the main address includes a main sector address and a page address. The main sector address indicates the initial storage location of the data in the Nandflash buffer. The page address indicates the initial storage location of the data in the Nandflash storage area.
The spare address includes a spare sector address, for indicating the initial storage location of checksum data corresponding to the data in the Nandflash buffer.
Block 2: The Nandflash controller sends a precoded command, the main address and the spare address to the Nandflash, writes data of one sector into the main area of the Nandflash according to the main address. Meanwhile, an Error Checking and Correcting (ECC) device in the Nandflash controller starts to perform encoding operation, to generate the checksum data.
Block 3: When all data of a sector is transmitted to the main area, the encoding operation of the ECC device is finished at the same time. The Nandflash controller writes the checksum data generated into the spare area of the Nandflash according to the spare address.
The specific execution sequence of blocks 2 and 3 has been explicitly defined in the conventional criterions.
After writing the checksum data in block 3, the Nandflash controller returns a transmission completion flag to the CPU. The CPU configures the command for the next write operation, and then returns to block 1, until the data to be written is transmitted.
Supposing that the Nandflash buffer is full after the Nandflash controller executes the above blocks 1-3 for several times. However, the not all data to be written has been transmitted. And then, a write operation command is first sent to the Nandflash between blocks 2 and 3, when executing blocks 1-3 again. The Nandflash reads the data from the buffer and writes the data in the storage area for storage according to the page address. Then, the Nandflash controller starts to execute block 3. It is supposed that the Nandflash buffer is not full, after the Nandflash controller executes the blocks 1-3 repeatedly. However, all data to be written has been transmitted. A write operation command is sent to the Nandflash. The Nandflash writes data in the whole buffer into the storage area according to the page address. However, all data in the un-written part of the buffer is FFn by default. It can be seen that, sector operation of the Nandflash is based on the size of one page, that is, the sector operation is based on size of the buffer.
2) Data Transmission During Read Operation:
FIG. 1b is a flow chart illustrating a method for reading data in the prior art.
Block 1: The Nandflash controller receives a read operation command and command parameters from the CPU. The read operation command indicates that the current transmission type is the read operation, and the command parameters configured by the CPU include a main address and a spare address.
The main address and the spare address in the block are same as those introduced above.
Block 2: The Nandflash controller sends a precoded command, the main address and the spare address to the Nandflash. And then, the Nandflash controller waits for the Nandflash to write data of a whole page into the buffer according to the page address. During executing the read operation, the Nandflash first pulls down its RB pin, and pulls up the pin after completing the read operation. The Nandflash needs not to wait, until all the data written into the buffer is read out by the Nandflash.
Block 3: The Nandflash controller reads data of one sector from the Nandflash buffer according to the main sector address. Meanwhile, the ECC device in the Nandflash controller starts to perform encoding to generate the checksum data. The encoding is completed while the reading operation is finished.
Block 4: The Nandflash controller reads the checksum data from the Nandflash buffer according to the spare sector address.
The specific execution sequence of blocks 3 and 4 has been explicitly defined in the conventional criterions.
After finishing block 4, the Nandflash controller decodes the checksum data read and the checksum data generated by the ECC device. If an error is found, the error address and error location are calculated and reported to the CPU. After performing error correction, the CPU configures the next read operation command, and then returns to block 1, until all the data to be read is read out.
If the data transmission process of above Nandflash controller is described at a logic level, a common state machine concept in the logic design is adopted. FIG. 1 is a flow chart illustrating a state machine of the Nandflash controller in the conventional method. The flowing illustrates the data transmission of the above read operation and write operation. Each box represents a state.
Although in the conventional method, the read and write operations in the data transmission of the Nandflash controller are simple and clear, every time one sector is finished, it is required to switch to the CPU from the Nandflash controller to configure commands for next sector operation. As for the state machine, every time the operation of one sector is finished, it is required to configure parameters for the state machine and start up the next state machine. Thus, it is necessary to start up the state machine for many times to complete the data transmission of one page, which costs much time and occupies extra clock resources, thus reduces the data transmission efficiency.